The employment of a P-type polysilicon thin film transistor for the active load in the static random access memory (SRAM) can bring about several advantages, which include the lower standby current, the improved cell stability and the higher soft-error immunity. A typical polysilicon thin film transistor comprises two opposite polysilicon layers separated by a gate oxide layer which is formed by the oxidation of the bottom layers of the two opposite polysilicon layers. The film quality of the silicon dioxide layer formed by the oxidation of the polysilicon is much inferior to the film quality of the silicon dioxide layer which is formed by the oxidation of the single-crystalline silicon substrate. With a view to overcoming such a quality problem as described above, James R. Pfiester, et al. in their article, entitled "A Novel PMOS SOI Polysilicon Transistor", IEEE ELECTRON DEVICE LETTERS, VOL. 11, NO. 8, AUGUST 1990, PP. 349-351, proposed a method for fabricating a polysilicon transistor, in which the gate oxide is formed over the single-crystal silicon substrate, with the substrate acting as the gate electrode.
As illustrated in FIGS. 1a-1d, the method proposed by James R. Pfiester, et al. comprises a first step in which silicon dioxide serving as the gate oxide 11 is thermally grown on the N-type single-crystalline silicon substrate 10. Thereafter, an undoped layer of amorphous silicon thin film is formed by deposition at a temperature of 550.degree. C. The amorphous silicon thin film is then transformed to a polysilicon layer by a 600.degree. C. annealing for 12 hours before the polysilicon layer is implanted with phosphorous ions to form an N.sup.- -type polysilicon thin film 12, as shown in FIG. 1a. A silicon nitride layer 13 is subsequently deposited on the N.sup.- -type polysilicon thin film 12. The silicon nitride layer 13 is then coated thereon with a photoresist 14 which is used in forming a patterned silicon nitride layer by photolithography and reactive ion etching. Prior to the stripping of the photoresist 14, a high-energy boron implantation is performed through a naked N.sup.- -type polysilicon channel and the gate oxide 11 and into the underlying silicon substrate 10 so as to form the P.sup.+ buried-gate electrode 15, as shown in FIG. 1b.
After the photoresist 14 is stripped, the patterned silicon nitride layer 13 is used as a mask in growing a polysilicon oxide 16 on the naked N.sup.- -type polysilicon channel region. In the meantime, the polysilicon channel region is made thinner, as shown in FIG. 1C. Upon completion of the stripping of the silicon nitride mask 13, the P.sup.+ -type drain 17 and source 18 regions are formed by using a blanket boron implantation, thereby defining the active regions. This P.sup.+ implant is prevent from entering the underlying N.sup.- -type polysilicon channel region due to the presence of the thick polysilicon oxide 16. The P.sup.+ -type drain/source regions 17 and 18 are then annealed at a temperature of 850.degree. C. for 15 minutes, as illustrated in FIG. 1d.
The deposition of a silicon dioxide layer serving as an intermediate insulation and the definition of contact holes and aluminum metallization are carried out by using the conventional CMOS process. Finally, the drain electrode and the source electrode are formed by etching aluminum in conjunction with the photolithography.
The method proposed by James R. Pfiester, et al. as described above is defective in design in that it is more complicated than the conventional methods for fabricating a polysilicon thin film transistor, and that it is therefore not cost-effective.